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| digital input stereo, 2 w, class-d audio power amplifier data sheet SSM2518 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features filterless, digital input class-d amplifier serial digital audio interface supports common formats i 2 s, left justified, right justified, tdm1-16, and pcm 2 channels 2 w into 4 and 2 channels 1.4 w into 8 with 1% thd+n, when using a 5 v supply i 2 c control interface or standalone operation 91% efficiency at full scale into an 8 load 97 db signal-to-noise ratio (snr), a-weighted 80 db power supply rejection ratio (psrr) at 217 hz digital volume control: ?71.25 db to +24 db in 0.375 db steps supports a wide range of sample rates from 8 khz to 96 khz automatic sample rate detection can operate using 64 f s bclk as the mclk source 2.5 v to 5.5 v speaker supply voltage (pvdd) 1.62 v to 3.6 v digital supply voltage (dvdd) pop-and-click suppression short-circuit and thermal protection with programmable autorecovery smart power-down when no input signal is detected power-on reset low power modes for performance/power trade-offs user selectable ultralow emi emission mode programmable dynamic range compression (drc) with noise gate, expander, compressor, and limiter available in two packages 16-bump, 2.2 mm 2.2 mm, 0.5 mm pitch wlcsp 20-lead, 4.0 mm 4.0 mm lfcsp applications mobile phones portable media players laptop pcs wireless speakers portable gaming small lcd televisions navigation systems general description the SSM2518 is a digital input, class-d power amplifier that com- bines a digital-to-analog converter (dac) and a sigma-delta (-) class-d modulator. this unique architecture enables extremely low real-world power consumption from digital audio sources with excellent audio performance. the SSM2518 is ideal for power sensitive applications, such as mobile phones and portable media players, where system noise can corrupt small analog signals such as those sent to an analog input audio amplifier. using the SSM2518 , audio data can be transmitted to the amplifier over a standard digital audio serial interface, thereby significantly reducing the effect of noise sources such as gsm interference or other digital signals on the transmitted audio. the closed-loop digital input design retains the benefits of an all digital amplifier, yet enables very good psrr and audio performance. the three level, - class-d modulator is designed to provide the least amount of emi interference, the lowest quiescent power dissi- pation, and the highest audio efficiency without sacrificing audio quality. input is provided via a serial audio interface, programmable to accept all common audio formats including i 2 s and tdm. control of the ic is provided via an i 2 c control interface. the SSM2518 can accept a variety of input mclk frequencies and can use bclk as the clock source in some configurations. additional features include a soft digital volume control, de- emphasis, and a programmable digital dynamic range compressor. the architecture of the SSM2518 provides a solution that offers lower power and higher performance than existing dac plus class-d solutions. its digital interface also offers a better system solution for other products whose sole audio source is digital, such as wireless speakers, laptop pcs, portable digital televisions, and navigation systems. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2518 data sheet rev. a | page 2 of 48 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 3 functional block diagram .............................................................. 4 specifications..................................................................................... 5 performance specifications......................................................... 5 power supply requirements ....................................................... 6 digital input/output.................................................................... 6 digital interpolation filter .......................................................... 6 digital timing............................................................................... 7 absolute maximum ratings ....................................................... 8 thermal resistance ...................................................................... 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 14 power supplies ............................................................................ 14 power-down modes .................................................................. 14 power-on reset/voltage supervisor........................................ 14 master and bit clock.................................................................. 14 typical application circuit ........................................................... 16 digital audio interface .................................................................. 17 channel mapping ....................................................................... 17 sample rate detection............................................................... 17 standalone mode........................................................................ 17 low power modes ...................................................................... 17 dynamic range control............................................................ 17 mute options .............................................................................. 18 volume control .......................................................................... 18 de-emphasis filter ..................................................................... 18 analog gain ................................................................................ 18 fault detection and recovery................................................... 19 digital audio formats ................................................................... 20 stereo mode ................................................................................ 20 tdm, 50% duty cycle mode ................................................... 20 tdm, pulse mode ...................................................................... 20 pcm, multichannel mode ........................................................ 21 pcm mono mode ...................................................................... 21 i 2 c configuration interface .......................................................... 22 overview ..................................................................................... 22 register summary (reg_map) .................................................. 25 register (reg_map) details ....................................................... 26 software reset and master software power-down control register ........................................................................................ 26 edge speed and clocking control register............................ 27 serial audio interface and sample rate control register.... 28 serial audio interface control register .................................. 29 channel mapping control register......................................... 30 left channel volume control register................................... 31 right channel volume control register ................................ 32 volume and mute control register......................................... 33 fault control 1 register............................................................. 34 power and fault control register ............................................ 35 drc control 1 register............................................................. 36 drc control 2 register............................................................. 37 drc control 3 register............................................................. 38 drc control 4 register............................................................. 40 drc control 5 register............................................................. 41 drc control 6 register............................................................. 42 drc control 7 register............................................................. 44 drc control 8 register............................................................. 45 drc control 9 register............................................................. 46 packaging and ordering information ......................................... 47 outline dimensions................................................................... 47 ordering guide .......................................................................... 48 www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 3 of 48 revision history 12 /11rev. 0 to rev. a added lfcsp...................................................................... universal changes to features section ............................................................1 changes to table 1, supply current parameter ............................5 changes to table 3, input voltage parameter................................6 changes to table 7 ............................................................................8 added figure 5 and table 9, renumbered sequentially ............10 changes to power-down modes section.....................................14 changes to master and bit clock section....................................14 changes to sample rate detection section.................................17 10/11revision 0: initial version www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 4 of 48 functional block diagram lrclk bclk sdata mclk sda scl sd outl+ outl? outr+ outr? dvdd sa_mod pvdd gnd addr power-on reset i 2 s i 2 c clocking power control volume control drc dac full bridge power stage full bridge power stage - ? class-d modulator 10242-001 figure 1. www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 5 of 48 specifications all specifications at pvdd = 5.0 v, dvdd = 1.8 v, f s = 48 khz, mclk = 128 f s , t a = 25c, r l = 8 + 15 h, lp_mode = 0, volume control = 0 db, unless otherwise noted. performance specifications table 1. parameter symbol test conditions/comments min typ max unit device characteristics p o f = 1 khz, bw = 20 khz output power r l = 4 , thd = 1%, pvdd = 5.0 v 2 w r l = 4 , thd = 10%, pvdd = 5.0 v 2.5 w r l = 8 , thd = 1%, pvdd = 5.0 v 1.42 w r l = 8 , thd = 10%, pvdd = 5.0 v 1.8 w r l = 4 , thd = 1%, pvdd = 3.6 v 1.3 w r l = 4 , thd = 10%, pvdd = 3.6 v 1.7 w r l = 8 , thd = 1%, pvdd = 3.6 v 0.75 w r l = 8 , thd = 10%, pvdd = 3.6 v 0.94 w r l = 4 , thd = 1%, pvdd = 2.5 v 0.4 w r l = 4 , thd = 10%, pvdd = 2.5 v 0.45 w r l = 8 , thd = 1%, pvdd = 2.5 v 0.275 w r l = 8 , thd = 10%, pvdd = 2.5 v 0.35 w efficiency p o = 1.4 w, 8 , pvdd = 5.0 v, normal operation 91 % p o = 1.4 w, 8 , pvdd = 5.0 v, ultralow emi operation 86 % thd + n p o = 0.5 w into 8 each channel, f = 1 khz, pvdd = 5 v 0.04 % total harmonic distortion plus noise p o = 0.25 w into 8 each channel, f = 1 khz, pvdd = 3.6 v 0.03 % channel separation x talk p o = 1 w, f = 1 khz, pvdd = 5 v 108 db average switching frequency f sw 280 khz differential output offset v oos 2.0 mv power supply rejection ratio psrr dc pvdd = 2.5 v to 5.0 v 70 80 db psrr gsm v ripple = 100 mv rms at 217 hz, dither input 80 db psrr gsm v ripple = 100 mv rms at 217 hz, no input 100 db supply current i pvdd dither input, no load, pvdd = 5.0 v 4.7 ma pvdd dither input, no load, pvdd = 3.6 v 4.4 ma dither input, no load, pvdd = 2.5 v 3.8 ma software power-down, sd = 1.8 v, spwdn = 1, pvdd = 3.6 v 4 a hardware power-down, sd = 0 v, pvdd = 3.6 v 100 na dvdd i dvdd dither input, no load, dvdd = 3.3 v 3.0 ma dither input, no load, dvdd = 1.8 v 1.5 ma dither input, no load, dvdd = 1.8 v, f s = 8 khz 0.25 ma software power-down, sd = 1.8 v, spwdn = 1, dvdd = 1.8 v 2.5 a hardware power-down, sd = 0 v, dvdd = 1.8 v 100 na output noise voltage e n pvdd = 5 v, f = 20 hz to 20 khz, dither input, a-weighted 50 v pvdd = 3.6 v, f = 20 hz to 20 khz, dither input, a-weighted 40 v signal-to-noise ratio snr a-weighted, refe rred to 0 dbfs, pvdd = 3.6 v 97 db mute attenuation soft mute on 100 db www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 6 of 48 power supply requirements table 2. parameter min typ max unit pvdd 2.5 3.6 5.5 v dvdd 1.62 1.8 3.6 v digital input/output table 3. parameter min typ max unit test conditions/comments input voltage high (v ih ) 0.7 dvdd 3.6 v addr, mclk, bclk, lrclk, sdata, samod 1.35 5.5 v sd , sda, scl low (v il ) ?0.3 +0.3 dvdd v addr, mclk, bclk, lrclk, sdata, samod ?0.3 +0.35 v sd , sda, scl input leakage current high (i ih ) 1 a excluding mclk low (i il ) 1 a excluding mclk and bidirectional pin mclk input leakage current high (i ih ) 3 a low (i il ) 3 a input capacitance 5 pf digital interpolation filter table 4. parameter factor min typ 1 max unit pass band ?3 db 0.4535 f s 22 khz ripple 0.01 db transition band 0.5 f s 24 khz stop band 0.5465 f s 26 khz attenuation 70 db group delay 25/f s 521 s 1 typical value given for 48 khz sample rate. www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 7 of 48 digital timing all timing specifications are given for the default setting (i 2 s mode) of the serial input port. table 5. limit parameter min max unit description master clock t mp 74 136 ns mclk period, 256 f s mode (mcs = b0010) t mp 148 271 ns mclk period, 128 f s mode (mcs = b0001) serial port t bil 40 ns bclk low pulse width t bih 40 ns bclk high pulse width t lis 10 ns setup time from lrclk or sdata edge to bclk rising edge t lih 10 ns hold time from bclk rising edge to lrclk or sdata edge t sis 10 ns sdata setup time to bclk rising t sih 10 ns sdata hold time from bclk rising i 2 c port f scl 400 khz scl frequency t sclh 0.6 s scl high t scll 1.3 s scl low t scs 0.6 s setup time; relevant for repeated start condition t sch 0.6 s hold time; after this period, the first clock is generated t ds 100 ns data setup time t scr 300 ns scl rise time t scf 300 ns scl fall time t sdr 300 ns sda rise time t sdf 300 ns sda fall time t bft 0.6 s bus-free time (time between stop and start) digital timing diagrams t sis t sih t sis t sih t lih t bp t bih bclk lrclk sdata left-justified mode sdata i 2 c-justified mode sdata right-justified mode t bil t lis t sis t sih t sis t sih msb msb msb lsb msb ? 1 10242-002 figure 2. serial input port timing t sch t scs t bft t scf t ds t scll t scr t sclh t sch stop condition start condition s d a scl 10242-003 figure 3. i 2 c port timing www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 8 of 48 absolute maximum ratings absolute maximum ratings apply at 25c, unless otherwise noted. table 6. parameter rating pvdd supply voltage ?0.3 v to +6 v dvdd supply voltage ?0.3 v to +3.6 v input voltage (addr, mclk, bclk, lrclk, sdata, samod pins) ?0.3 v to +3.6 v input voltage ( sd , sda, and scl pins) ?0.3 v to +6 v esd susceptibility 4 kv storage temperature range ?65c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +165c lead temperature (soldering, 60 sec) 300c stresses abo v ethose listedunderabsolutemaximumratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximumratingconditionsfor extendedperiodsmayaffect de v ice reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 7. thermal resistance package type ja unit 16-ball, 2 mm 2 mm wlcsp 56 c/w 20-lead, 4.0 mm 4.0 mm lfcsp 54 c/w esd caution www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 9 of 48 pin configuration and fu nction descriptions top view (ball side down) not to scale 1 a b c d 234 ball a1 indicator outr+ outr? dvdd sdata pvdd addr scl bclk outl+ outl? sda mclk gnd sd samod lrclk 10242-009 figure 4. wlcsp pin configuration table 8. pin function descriptions, wlcsp pin no. mnemonic function 1 description a1 outr+ o right channel output positive. b1 outr? o right channel output negative. a4 outl+ o left channel output positive. b4 outl? o left channel output negative. a3 pvdd p 2.5 v to 5.5 v amplifier power. a2 gnd p amplifier ground. c1 dvdd p 1.62 v to 3.6 v digital and analog power. b2 sd i power-down control, active low. c3 scl i i 2 c clock. c4 sda i/o i 2 c data. d4 mclk i serial audio interface master clock. d2 lrclk i i 2 s word clock. d3 bclk i i 2 s bit clock. d1 sdata i i 2 s serial data. c2 samod i standalone/i 2 c mode select. high = standalone mode, low = i 2 c mode. b3 addr i i 2 c address select. 1 i is input, o is output, i/o is input/output, and p is power. www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 10 of 48 pin 1 indicator 1 outl+ notes 1. connect the exposed pad to gnd. 2 outl? 3 addr 4 sda 5 scl 13 sd 14 outr? 15 outr+ 12 dvdd 11 samod 6 mclk 7 bclk 8 gnd 10 sdata 9 lrclk 18 gnd 19 gnd 20 pvdd 17 gnd 16 pvdd top view (not to scale) SSM2518 10242-110 figure 5. lfcsp pin configuration table 9. pin function descriptions, lfcsp pin no. mnemonic function 1 description 1 outl+ o left channel output positive. 2 outl? o left channel output negative. 3 addr i i 2 c address select. 4 sda i/o i 2 c data. 5 scl i i 2 c clock. 6 mclk i serial audio interface master clock. 7 bclk i i 2 s bit clock. 8 gnd p amplifier ground. 9 lrclk i i 2 s word clock. 10 sdata i i 2 s serial data. 11 samod i standalone/i 2 c mode select. high = standalone mode, low = i 2 c mode. 12 dvdd p 1.62 v to 3.6 v digital and analog power. 13 sd i power-down control, active low. 14 outr? o right channel output negative. 15 outr+ o right channel output positive. 16 pvdd p 2.5 v to 5.5 v amplifier power. 17 gnd p amplifier ground. 18 gnd p amplifier ground. 19 gnd p amplifier ground. 20 pvdd p 2.5 v to 5.5 v amplifier power. 1 i is input, o is output, i/o is input/output, and p is power. www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 11 of 48 typical performance characteristics 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) output power (w) 2.5v 3.6v 5.0v gain = 5v mclk = 256 f s r l = 8 ? , 33h 10242-011 figure 6. thd + n vs. output power into 8 , 5.0 v gain setting 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) output power (w) 2.5v 3.6v 5.0v gain = 5v mclk = 256 f s r l = 4 ? , 15h 10242-012 figure 7. thd + n vs. output power into 4 , 5.0 v gain setting 10 100 1k 10k 100k frequency (hz) 0.25w 0.5w 1.0w 0.01 0.1 1 10 100 thd + n (%) 10242-013 pvdd = 5v gain = 5v mclk = 256 f s r l = 8 ? , 33h figure 8. thd + n vs. frequency, pvdd = 5 v, r l = 8 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) output power (w) 2.5v 3.6v 5.0v 10242-014 gain = 3.6v mclk = 256 f s r l = 8 ? , 33h figure 9. thd + n vs. output power into 8 , 3.6 v gain setting 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) output power (w) 2.5v 3.6v 5.0v gain = 3.6v mclk = 256 f s r l = 4 ? , 15h 10242-015 figure 10. thd + n vs. output power into 4 , 3.6 v gain setting 10 100 1k 10k 100k frequency (hz) 0.25w 0.5w 1.0w 0.01 0.1 1 10 100 thd + n (%) 10242-016 pvdd = 5v gain = 5v mclk = 256 f s r l = 4 ? , 15h figure 11. thd + n vs. frequency, pvdd = 5 v, r l = 4 www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 12 of 48 10 100 1k 10k 100k frequency (hz) 0.125w 0.25w 0.5w 0.01 0.1 1 10 100 thd + n (%) 10242-017 pvdd = 3.6v gain = 3.6v mclk = 256 f s r l = 8 ? , 33h figure 12. thd + n vs. frequency, pvdd = 3.6 v, r l = 8 10 100 1k 10k 100k frequency (hz) 0.01 0.1 1 10 100 thd + n (%) 0.05w 0.10w 0.20w 10242-018 pvdd = 2.5v gain = 3.6v mclk = 256 f s r l = 8 ? , 33h figure 13. thd + n vs. frequency, pvdd = 2.5 v, r l = 8 4 5 6 7 8 9 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 quiescent current (ma) supply voltage (v) no load 8 ? + 33h 4 ? + 33h dac_lpm = 1 amp_lpm = 1 dvdd = 1.8v dither input 10242-019 figure 14. quiescent current (power stage) vs. supply voltage 10 100 1k 10k 100k frequency (hz) 0.125w 0.25w 0.5w 0.01 0.1 1 10 100 thd + n (%) 10242-020 pvdd = 3.6v gain = 3.6v mclk = 256 f s r l = 4 ? , 15h figure 15. thd + n vs. frequency, pvdd = 3.6 v, r l = 4 10 100 1k 10k 100k frequency (hz) 0.01 0.1 1 10 100 thd + n (%) 0.05w 0.10w 0.20w 10242-021 pvdd = 2.5v gain = 3.6v mclk = 256 f s r l = 4 ? , 15h figure 16. thd + n vs. frequency, pvdd = 2.5 v, r l = 4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.6 2.0 2.4 2.8 3.2 3.6 quiescent current (ma) supply voltage (v) 8khz 256 f s 24khz 256 f s 48khz 256 f s mclk = 256 f s dac_lpm = 1, amp_lpm = 1 10242-022 figure 17. quiescent current (digital core) vs. supply voltage www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 13 of 48 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.5 3.0 3.5 4.0 4.5 5.0 output power ( w) supply voltage (v) gain = 5v r l = 8 ? , 33h 1khz 10175-026 1% 5% 10% 0 0.5 1.0 1.5 2.0 2.5 2.5 3.0 3.5 4.0 4.5 5.0 output power (w) supply voltage (v) 1% 5% 10% gain = 5v r l = 4 ? , 15h 1khz 10242-024 figure 18. maximum output power vs. supply voltage, r l = 4 figure 21. maximum output power vs. supply voltage, r l = 8 0 10 20 30 40 50 60 70 80 90 100 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 efficiency (%) combined output power, both channels (w) 5v 3.6v 2.5v r l = 8 ? + 33 10175-029 0 10 20 30 40 50 60 70 80 90 100 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 efficiency (%) combined output power, both channels (w) 5v 3.6v 2.5v r l = 4 ? , 15 10242-028 figure 22. efficiency vs. output power into 8 figure 19. efficiency vs. output power into 4 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k pvdd = 2.5v pvdd = 3.6v pvdd = 5v psrr (db) frequency (hz) 10242-030 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 200 2k frequency (hz) crosstalk (db) 20k pvdd = 5v r l = 8 ? , 33 h p o = 100mw left to right right to left 10242-027 figure 23. psrr vs. frequency figure 20. crosstalk vs. frequency www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 14 of 48 theory of operation the SSM2518 is fully integrated 2-channel digital input, class-d output audio amplifier. the SSM2518 receives digital audio input and produces the pdm differential switching outputs using the internal power stage. the part has built in protection for over- temperature as well as overcurrent conditions. the SSM2518 also has built in soft turn on and soft turn off for pop-and-click suppression. the part has programmable register control via the i 2 c port. power supplies the SSM2518 requires two power supplies: pvdd and dvdd. descriptions of each of these supplies follow. pvdd the pvdd pin supplies power to the full bridge power stage of a mosfet and its associated drive, control, and protection circuitry. pvdd can operate from 2.5 v to 5.5 v and must be present to obtain audio output. lowering the supply pvdd results in lower output power and, correspondingly, lower power consumption but does not degrade audio performance. dvdd the dvdd pin provides power to the digital logic circuitry and determines the input trip points. dvdd can operate from 1.62 v to 3.6 v and must be present to obtain audio output. lowering the supply voltage of dvdd results in lower power consump- tion but does not affect audio performance. power-down modes the SSM2518 offers a hardware shutdown pin, sd , which can be used to set the ic to its lowest power state, with all blocks disabled. this hardware shutdown mode is enabled when the sd pin is pulled low. when the hardware shutdown is removed, the ic begins in software power-down mode, where all blocks except for the i 2 c interface are disabled. to fully power up the amplifier, clear s_rst (bit 7 of register 0x00). in addition to the software power-down, the software master mute is enabled at the initial state of the amplifier; therefore, no audio is output until bit 0 of register 0x07 is cleared. the left and right channels can be independently shut down by setting setting l_pwdn and r_pwdn (bit 1 and bit 2, respectively, in register 0x09). disabling a channel shuts down the channel specific digital processing, dac, class-d modulator, and power stage. the SSM2518 also contains a smart power-down feature, which is enabled by default. this feature can be disabled by clearing apwdn_en (bit 0 in register 0x 09). when active, this feature monitors the incoming digital audio signal. if this is zero for 1024 consecutive samples, regardless of sample rate, it puts the ic in the smart power-down state wherein all blocks, except the i 2 s and i 2 c ports, are placed in a low power state. once a single nonzero input is received on the i 2 s interface, the SSM2518 leaves this state and resumes normal operation. power-on reset/voltage supervisor the SSM2518 includes an internal power-on reset and voltage supervisor circuit. this circuit provides an internal reset to all circuitry whenever pvdd or dvdd is substantially below the nominal operating threshold. this circuit simplifies supply sequencing during initial power-on. the circuit also monitors the power supplies to the SSM2518 . if the supply voltages fall below the nominal operating threshold, this circuit stops the output and issues a reset. this ensures that no damage occurs due to low voltage operation and that no pops can occur under nearly any power removal condition. master and bit clock the SSM2518 requires an internal master clock to operate. this clock must run at a frequency between 2.048 mhz and 6.144 mhz, depending on the input sample rate, and it must be fully synchro- nous with the incoming audio data. this clock signal can be derived from either the mclk or bclk pin, depending on the configuration used. if the mclk pin is used, the internal clock is derived by either dividing, passing through, or doubling the external clock signal as required. the clock supplied to the mclk pin can range from 2.048 mhz to 38.864 mhz. in this case, the external mclk pin signal can run at various multiples of the audio sample rate (f s ). the relationship between the mclk rate and the audio sample rate is determined by the master clock select (mcs) register setting, bits[4:1] in register 0x00. table 11 provides a summary of the available options. in addition, a bit clock must run at the same rate as the incoming audio data on the sdata pin. this clock can be supplied to the bclk pin, or it can be generated internally by dividing mclk. in this case, when bclk_gen (bit 7 of register 0x03) is set, the logic level of the bclk pin is used to select the audio interface bclk rate. tie the bclk pin to dvdd for 16 clock cycles per channel; tie it to ground for 32 cycles per channel. if the system bit clock is in the range of acceptable internal master clock frequencies (between 2.048 mhz and 6.144 mhz), then it can serve as both master clock and bit clock. setting no_bclk (bit 5 of register 0x00) routes the signal on the www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 15 of 48 mclk pin to serve as the internal bit clock as well. in this case, tie the bclk pin to ground. once the SSM2518 has entered its power-down state, it is possible to gate the clocks to conserve system power. however, a valid master clock must be present for the audio amplifier to operate. it is best to use a low jitter clock (less than 1 ns peak- to-peak) to ensure the specified audio performance. www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 16 of 48 typical application circuit 100nf *optional for applications with >20cm speaker cable. SSM2518 4.7f pvdd 2.5v to 5.5v c3 470pf 2.2k ? 2.2k ? c4 470pf fb4 fb3 c1 470pf c2 470pf fb2 fb1 * 100nf audio processor system microcontroller dvdd 1.62v to 3.6v 1.35v to 5.5v gnd addr samod sd scl mclk lrclk bclk dvdd pvdd outl+ outl? outr+ outr? sdata sda 10242-039 figure 24. typical application circuit using i 2 c configuration www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 17 of 48 digital audio interface the SSM2518 operates as a slave on the serial audio interface. it is capable of receiving stereo i 2 s-style, left justified, or right ju stified data. mono, stereo, and multichannel pcm/tdm interface formats are available. the data format and interface style are selected by adjusting the sdata_fmt and sai fields in register 0x02. note that, when operating in right justified mode, the proper data width must be chosen. the function of the lrclk pin varies depending on the data format. see figure 26 through figure 30 for the expected audio formats for various configurations. channel mapping stereo audio formats and tdm formats with 2, 4, 8, or 16 channels are available. in these modes, the amplifier left and right audio can be independently chosen from any of the available channels using the two fields in register 0x04. for most digital interface formats, many of these options are not present. for example, in stereo modes, only channel 0 and channel 1 are valid, and in four-slot tdm mode, only channel 0, channel 1, channel 2, and channel 3 are valid. sample rate detection the SSM2518 can be configured to automatically detect the sample rate, or the sample rate can be entered manually into the fs field (bit 1 and bit 0 of register 0x02). the choice of automatic or manual sample rate detection is made by setting the asr bit (bit 0 of register 0x01). sample rate detection functions properly only when mcs (bits[4:1] of register 0x00) is set correctly. standalone mode when the samod pin is pulled high, the SSM2518 can operate in several common stereo formats without any i 2 c control. some details of the serial audio interface can be configured by tying the unused i 2 c pins to ground or dvdd, as shown in tabl e 10 . in addition, the amplifier gain can be controlled via the addr pin. table 10. standalone mode pin functions pin standalone function pin options scl format low: i 2 s high: left justified sda mclk_sel low: mclk = 256 f s high: mclk = 384 f s sd sd low: shutdown/mute high: normal operation addr gain low: +12 db digital gain high: 0 db digital gain in standalone mode, the volume control, dynamic range control, and emi control features are disabled. automatic sample rate detection and smart power-down are enabled. all other settings are set to their default values. low power modes two low power modes are available. if dac_lpm (bit 3 of register 0x09) is set, the digital-to-analog converter (dac) runs at half speed, reducing the quiescent current. this half speed mode is also active when the mcs setting (bits[4:1] of register 0x00) is set to its lowest value (mcs = 0000) because the slowest acceptable mclk rates can only support half speed dac operation. if amp_lpm (bit 4 of register 0x09) is set, the - modulator runs in a special mode that offers lower quiescent current when the output power is small, at the expense of slightly degraded audio performance. dynamic range control the dynamic range control, or drc, can be used to reduce the dynamic range of the audio signal. a common drc scheme involves applying a gain reduction to large output signals, along with a net increase in gain for moderate to small signals. the qualitative result is a louder speaker output for moderate output levels without the undesired effects of amplifier clipping or speaker overdrive at high levels. to calculate the gain adjustment, an rms detector gives the average level of the input signal, based on the averaging time set by rms_tav (bits[3:0] in register 0x12). based on this time averaged level, the overall gain is adjusted so that the input/ output characteristic matches the specified compression curve. this curve can be represented by a log-to-log graph with five distinct regions, as shown in figure 25 . output input without drc with drc nt et ct lt smax ct et smin without drc with drc 10242-032 figure 25. drc compression curve: lo g-to-log representation of the drc output level vs. input level from bottom left to top right, these regions (shown in red) are the noise gate, expander, linear region, compressor, and limiter. the control points between these regions can be set using the drc control registers (register 0x0a through register 0x12) using the variable names (ct, et, and so forth) as shown on the plot axes in figure 25 . each element can be individually enabled using the lim_en, comp_en, exp_en, and ng_en bits in www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 18 of 48 register 0x0a. the entire drc function can be enabled or disabled using drc_en (bits[1:0] of register 0x0a). linear region for input amplitudes between the drc_et and drc_ct thresholds, the drc attenuation is set to zero, that is, the input is passed straight through to the output. this is the region in the center of the compression curve (see figure 25 ) with a 1:1 slope, where the input and output amplitude are the same. compressor above the input level set by drc_ct (bits[3:0] of reg- ister 0x0c), the output amplitude does not rise as quickly as the input. this provides a smooth transition to the limiter region, where the output stops increasing altogether at the input level set by drc_lt (bits[7:4] of register 0x0c). at this point, the output level is drc_smax (bits[7:4] of register 0x0e). limiter when the input level is above the input level set by drc_lt, the output level does not exceed the level given by drc_smax (bits[7:4] of register 0x0e). instead, the overall gain is reduced to maintain that level without clipping. expander when the expander is enabled and the input level falls below the level set by drc_et (bits[7:4] of register 0x0d), the output level begins to decrease more rapidly than the input. this provides a smooth transition to the noise gate, where sufficiently small signals are blocked completely. when the input signal falls to the level set by drc_nt (bits[3:0] of register 0x0d), the output level is set by drc_smin (bits[3:0] of register 0x0e). noise gate when the noise gate is enabled and the input signal level falls below the threshold set by drc_nt for a period of time, the output is set to zero. set this at a level lower than all signals of interest to block the output in periods of silence. the period of time for which the input level must remain below the noise gate threshold prior to the output setting to zero is determined by hdt_ng, bits[3:0] of register 0x10. attack and decay rates to prevent audible distortion effects as the gain changes, the time constants for the attack (gain reduction) and decay (gain increase) are adjustable. the attack time is set by drc_att (bits[7:4] of register 0x0f), and the decay time is set by drc_dec (bits[3:0] of register 0x0f). between attack and decay, a hold time is used to prevent rapid switching between increased gain and decreased gain. the hold time is set by hdt_nor (bits[7:4] of register 0x10). post-drc gain because the drc feature may have an overall effect on the system gain, a separate digital gain option is provided to allow the user to compensate for this effect. this digital gain option is independent of the volume control feature, allowing an overall gain adjustment that remains separate from the volume settings. this level is set by drc_post_g (bits[5:2] of register 0x11). depending on the application, the entire drc block can be placed before or after the volume controls (l_vol and r_vol). this option is set by pre_vol (bit 6 of register 0x0a). mute options several mute options are available. each channel can be muted independently using the left channel mute (l_mute, bit 1 of register 0x07) or the right channel mute (r_mute, bit 2 of register 0x07). alternatively, both channels can be muted simultaneously using the master mute option (m_mute, bit 0 of register 0x07). the master mute is enabled at system startup; therefore, it must be disabled before any audio is produced. the SSM2518 also contains an automatic mute feature. this feature is enabled by setting amute (bit 7 of register 0x07). when active, this feature monitors the incoming digital audio signal. when the data stream is zero for 2048 consecutive frames (1024 stereo samples), the output is muted. when a single nonzero input is received on the i 2 s interface, the SSM2518 is unmuted and resumes normal operation. volume control the SSM2518 has a digital volume control that allows indepen- dent control of the left and right channels via registers 0x05 and 0x06, respectively. 255 levels are available, providing a range from +24 db to ?71.25 db in 0.375 db increments. this is a soft volume control, meaning that the gain is adjusted contin- uously from one value to another. this continuously adjusted gain prevents the audible pop that occurs with an instantaneous gain adjustment. when vol_link (bit 3 in register 0x07) is set, both channels are linked to the left channel volume setting. de-emphasis filter a digital de-emphasis filter is provided to compensate for the standard compact disc style preemphasis, which occurs in some audio systems. this filter is designed for use with a 44.1 khz sample rate only. to enable the de-emphasis filter, set deemp_en (bit 4 of register 0x07). analog gain the analog gain of the SSM2518 amplifier is set by ana_gain (bit 5 of register 0x07). each gain setting is designed to match the scaling needed for a specified pvdd voltage so that the digital full-scale values correspond to the clipping points of the amplifier at that voltage. if pvdd is larger than the voltage specified in this register, the digital scale does not fill the output voltage range and maximum output power is reduced. similarly, if pvdd is smaller than www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 19 of 48 specified in this register, analog clipping may occur within the range of possible digital codes. fault detection and recovery three fault conditions are detected by the SSM2518 fault detection system: left channel overcurrent, right channel overcurrent, and overtemperature. when any of these is detected, the amplifier shuts down and a read-only i 2 c bit is set to indicate the cause of the shutdown. the oc_l, oc_r, and ot fault indicators are bit 7, bit 6, and bit 5 (respectively) of register 0x08. an autorecovery feature can be enabled for temperature faults, current faults, or both, depending on the state of arcv (bit 1 and bit 0 of register 0x08). if autorecovery is enabled, the amplifier waits a short time (10 ms, 20 ms, 40 ms, or 80 ms) and attempts to recover. the recovery delay is set by ar_time (bit 7 and bit 6 of register 0x09). the maximum number of consecutive recovery attempts can be set to one, three, seven, or unlimited attempts; this number is set by max_ar (bit 3 and bit 2 of register 0x08). if the autorecovery feature is disabled or the maximum number of attempts has been reached, the amplifier remains shut down until a software reset or manual fault recovery attempt occurs. the manual fault recovery is triggered by setting the write-only bit, mrcv (bit 4 of register 0x08). www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 20 of 48 digital audio formats stereo mode sai = 0 sdata_fmt = 0 (i 2 s), 1 (lj), 2 (rj 24-bit), 3 (rj 16-bit) bclk left channel 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks any# bclks 8 to 32 bclks 8 to 32 bclks right channel right channel left channel 8 to 32 bclks left channel right channel lrclk sdata i2s sdata lj sdata rj 10242-004 figure 26. stereo modes: i 2 s, left justified, and right justified tdm, 50% duty cycle mode sai = 1 (2 slots), 2 (4 slots), 3 (8 slots), 4 (16 slots) sdata_fmt = 0 (i 2 s), 1 (lj), 2 (rj 24-bit), 3 (rj 16-bit) bclk_edge = 0 lrclk_mode = 0 slot_width = 0 (32 bclks), 1 (24 bclks), 2 (16 bclks) 32/24/16 bclks 32/24/16 bclks 32/24/16 bclks channel 1 channel 1 channel 2 channel 2 channel 2 channel n channel n channel n channel 1 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 24 or 16 bclks 24 or 16 bclks 24 or 16 bclks bclk lrclk s data i2s sdata lj sdata rj 10242-005 figure 27. tdm modes with 50% duty cycle lrclk tdm, pulse mode sai = 1 (2 slots), 2 (4 slots), 3 (8 slots), 4 (16 slots) sdata_fmt = 0 (i 2 s), 1 (lj), 2 (rj 24-bit), 3 (rj 16-bit) bclk_edge = 0 lrclk_mode = 1 slot_width = 0 (32 bclks), 1 (24 bclks), 2 (16 bclks) channel 2 channel n channel 1 32/24/16 bclks 32/24/16 bclks 32/24/16 bclks channel 1 channel 1 channel 2 channel 2 channel n channel n 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 24 or 16 bclks 24 or 16 bclks 24 or 16 bclks bclk lrclk s data i2s sdata lj sdata rj 10242-006 figure 28. tdm modes with pulse mode lrclk www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 21 of 48 pcm, multichannel mode sai = 1 (2 channels), 2 (4 channels), 3 (8 channels), 4 (16 channels) sdata_fmt = 0 (i 2 s), 1 (lj), 2 (rj 24-bit), 3 (rj 16-bit) bclk_edge = 1 lrclk_mode = 1 slot_width = 0 (32 bclks), 1 (24 bclks), 2 (16 bclks) channel 1 channel 1 channel 2 channel 2 channel 2 channel n channel n channel n 32/24/16 bclks 32/24/16 bclks 32/24/16 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks channel 1 24 or 16 bclks 24 or 16 bclks 24 or 16 bclks bclk lrclk s data i2s sdata lj sdata rj 10242-007 figure 29. multichannel pcm modes pcm mono mode sai = 5 sdata_fmt = 0 (i 2 s), 1 (lj), 2 (rj 24-bit), 3 (rj 16-bit) bclk_edge = 1 lrclk_mode = 1 mono channel 8 to 32 bclks mono channel 8 to 32 bclks mono channel 8 to 32 bclks any # bclks bclk lrclk sdata i2s sdata lj sdata rj 10242-008 figure 30. mono pcm modes www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 22 of 48 i 2 c configuration interface overview the SSM2518 supports a 2-wire serial (i 2 c-compatible) micro- processor bus driving multiple peripherals. two pins, serial data (sda) and serial clock (scl), carry information between the SSM2518 and the system i 2 c master controller. the SSM2518 is always a slave on the bus, meaning it cannot initiate a data transfer. each slave device is recognized by a unique device address. the device address byte format is shown in figure 31 . the address resides in the first seven bits of the i 2 c write. the lsb of this byte sets either a read or write operation. logic level 1 corresponds to a read operation, and logic level 0 corresponds to a write operation. the full byte addresses are shown in figure 3 , where the subaddresses are automatically incremented at word boundaries and can be used for writing large amounts of data to contiguous memory locations. this increment happens automatically after a single word write unless a stop condition is encountered. a data transfer is always terminated by a stop condition. both sda and scl should have a 2.2 k pull-up resistor on the lines connected to them. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 01101addr0r/w 10242-033 figure 31. i 2 c device address byte format addressing initially, each device on the i 2 c bus is in an idle state, monitoring the sda and scl lines for a start condition and the proper address. the i 2 c master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda while scl remains high. this indicates that an address/data stream follows. all devices on the bus respond to the start condition and shift the next eight bits (the 7-bit address plus the r/ w bit) msb first. the device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. the device address is determined by the state of the addr pin. this ninth bit is known as an acknowledge bit. all other devices withdraw from the bus at this point and return to the idle condition. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means that the master writes information to the peripheral, whereas a logic 1 means that the master reads information from the peripheral after writing the subaddress and repeating the start address. a data transfer takes place until a stop condition is encountered. a stop condition occurs when sda transitions from low to high while scl is held high. the timing for the i 2 c port is shown in . figure 3 stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, the SSM2518 immediately jumps to the idle condition. during a given scl high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the SSM2518 does not issue an acknowledge and returns to the idle condition. if the user exceeds the highest subaddress while in auto-increment mode, one of two actions is taken. in read mode, the SSM2518 outputs the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of a read. a no acknowledge condition is where the sda line is not pulled low on the ninth clock pulse of scl. if the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the SSM2518 , and the part returns to the idle condition. i 2 c read and write operations figure 33 shows the timing of a single word write operation. every ninth clock, the SSM2518 issues an acknowledge by pulling sda low. figure 34 shows the timing of a burst mode write sequence. this figure shows an example where the target destination registers are two bytes. the SSM2518 knows to increment its subaddress register every byte because the requested subaddress corresponds to a register or memory area with a byte word length. the timing of a single word read operation is shown in figure 35 . note that the first r/ w bit is 0, indicating a write operation. this is because the subaddress still needs to be written to set up the internal address. after the acknowledges the receipt of the subaddress, the master must issue a repeated start command followed by the chip address byte with the r/ SSM2518 w bit set to 1 (read). this causes the sda to reverse and begin driving data back to the master. the master then responds every ninth pulse with an acknowledge pulse to the . SSM2518 SSM2518 figure 36 shows the timing of a burst mode read sequence. this figure shows an example where the target destination registers are two bytes. the SSM2518 knows to increment its subaddress register every byte because the requested subaddress corresponds to a register or memory area with a byte word length. www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 23 of 48 sck sda start by master stop by master sck (continued) sda (continued) frame 3 data byte 1 frame 4 data byte 2 frame 1 chip address byte frame 2 subaddress byte ack ack ack ack r/w 10242-034 figure 32. i 2 c read/write timing start bit chip address (7 bits) data byte 1 (8 bits) stop bit r/w = 0 ack by slave subaddress (8 bits) ack by slave 10242-035 figure 33. single-word i 2 c write format data- word 1 data- word 2 r/w = 0 start bit chip address stop bit ack by slave subaddress ack by slave ack by slave ack by slave 10242-036 figure 34. burst mode i 2 c write format start bit r/w = 1 chip address data byte 1 stop bit r/w = 0 start bit chip address ack by slave subaddress ack by slave ack by master ack by slave 10242-037 figure 35. single-word i 2 c read format data- word 1 start bit r/w = 1 chip address r/w = 0 start bit chip address stop bit ack by slave subaddress ack by slave ack by master ack by slave 10242-038 figure 36. burst mode i 2 c read format www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 24 of 48 mclk frequency settings table 11. mcs bit field setting: mclk, ratio, and frequency input sample rate setting 0 b0000 1 setting 1 b0001 setting 2 b0010 setting 3 b0011 setting 4 b0100 setting 5 b0101 setting 6 b0110 setting 7 b0111 setting 8 b1000 8 khz ratio 256 f s 512 f s 1024 f s 1536 f s 2048 f s 3072 f s 400 f s 800 f s 1600 f s mclk 2.048 mhz 4.096 mhz 8.192 mhz 12.288 mhz 16.384 mhz 24.576 mhz 3.20 mhz 6.40 mhz 12.80 mhz 11.025 khz ratio 256 f s 512 f s 1024 f s 1536 f s 2048 f s 3072 f s 400 f s 800 f s 1600 f s mclk 2.822 mhz 5.6448 mhz 11.2896 mhz 16.9344 mhz 22. 5792 mhz 33.8688 mhz 4.41 mhz 8.82 mhz 17.64 mhz 12 khz ratio 256 f s 512 f s 1024 f s 1536 f s 2048 f s 3072 f s 400 f s 800 f s 1600 f s mclk 3.072 mhz 6.144 mhz 12.288 mhz 18.432 mhz 24. 576 mhz 38.864 mhz 4.80 mhz 9.60 mhz 19.20 mhz 16 khz ratio 128 f s 256 f s 384 f s 768 f s 1024 f s 1536 f s 200 f s 400 f s 800 f s mclk 2.048 mhz 4.096 mhz 8.192 mhz 12.288 mhz 16.384 mhz 24.576 mhz 3.20 mhz 6.40 mhz 12.80 mhz 22.05 khz ratio 128 f s 256 f s 512 f s 768 f s 1024 f s 1536 f s 200 f s 400 f s 800 f s mclk 2.822 mhz 5.6448 mhz 11.2896 mhz 16.9344 mhz 22. 5792 mhz 33.8688 mhz 4.41 mhz 8.82 mhz 17.64 mhz 24 khz ratio 128 f s 256 f s 512 f s 768 f s 1024 f s 1536 f s 200 f s 400 f s 800 f s mclk 3.072 mhz 6.144 mhz 12.288 mhz 18.432 mhz 24. 576 mhz 38.864 mhz 4.80 mhz 9.60 mhz 19.20 mhz 32 khz ratio 64 f s 128 f s 256 f s 384 f s 512 f s 768 f s 100 f s 200 f s 400 f s mclk 2.048 mhz 4.096 mhz 8.192 mhz 12.288 mhz 16.384 mhz 24.576 mhz 3.20 mhz 6.40 mhz 12.80 mhz 44.1 khz ratio 64 f s 128 f s 256 f s 384 f s 512 f s 768 f s 100 f s 200 f s 400 f s mclk 2.822 mhz 5.6448 mhz 11.2896 mhz 16.9344 mhz 22. 5792 mhz 33.8688 mhz 4.41 mhz 8.82 mhz 17.64 mhz 48 khz ratio 64 f s 128 f s 256 f s 384 f s 512 f s 768 f s 100 f s 200 f s 400 f s mclk 3.072 mhz 6.144 mhz 12.288 mhz 18.432 mhz 24. 576 mhz 38.864 mhz 4.80 mhz 9.60 mhz 19.20 mhz 96 khz ratio 64 f s 64 f s 128 f s 192 f s 256 f s 384 f s 50 f s 100 f s 200 f s mclk 3.072 mhz 6.144 mhz 12.288 mhz 18.432 mhz 24. 576 mhz 38.864 mhz 4.80 mhz 9.60 mhz 19.20 mhz 1 when using mcs = 0000, the chip automat ically operates in low power mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 25 of 48 register summary (reg_map) table 12. reg_map register summary reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 reset_power_control [7:0] s_rst reserved no_bclk mcs spwdn 0x05 rw 0x01 edge_clock_control [7:0] reserved edge asr 0x00 rw 0x02 serial_interface_sample_rate_control [7 :0] reserved sdata_fmt sai fs 0x02 rw 0x03 serial_interface_control [7:0] bclk_gen lrclk_mode lrclk_pol sai_msb slot_width bclk_edge reserved 0x00 rw 0x04 channel_mapping_control [7:0] ch_sel_r ch_sel_l 0x10 rw 0x05 left_volume_control [7:0] l_vol 0x40 rw 0x06 right_volume_control [7:0] r_vol 0x40 rw 0x07 volume_mute_control [7:0] amute reserved ana_ga in deemp_en vol_link r_mute l_mute m_mute 0x81 rw 0x08 fault_control_1 [7:0] oc_l oc_r ot mrcv max_ar arcv 0x0c rw 0x09 power_fault_control [7:0] ar_time reserved amp_lpm dac_lpm r_pwdn l_pwdn apwdn_en 0x99 rw 0x0a drc_control_1 [7:0] reserved pre_vol li m_en comp_en exp_en ng_en drc_en 0x7c rw 0x0b drc_control_2 [7:0] peak_att peak_rel 0x5b rw 0x0c drc_control_3 [7:0] drc_lt drc_ct 0x57 rw 0x0d drc_control_4 [7:0] drc_et drc_nt 0x89 rw 0x0e drc_control_5 [7:0] drc_smax drc_smin 0x8c rw 0x0f drc_control_6 [7:0] drc_att drc_dec 0x77 rw 0x10 drc_control_7 [7:0] hdt_nor hdt_ng 0x26 rw 0x11 drc_control_8 [7:0] reserved drc_post_g reserved 0x1c rw 0x12 drc_control_9 [7:0] reserved rms_tav 0x07 rw www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 26 of 48 register (reg_map) details software reset and master softwa re power-down control register address: 0x00, reset: 0x05, name: reset_power_control table 13. bit descriptions for reset_power_control bits bit name settings description reset access 7 s_rst software reset. write 1 to reset all internal blocks, including i 2 c registers, to their initial state. 0x0 rw 0 normal operation 1 software reset 6 reserved reserved. 0x0 rw 5 no_bclk bit clock source selection. either the mclk or bclk pin can be routed internally to the bit clock. 0x0 rw 0 bclk pin used as bit clock source. typical configuration. 1 mclk pin used as bit clock source . no bclk pin connection is needed. [4:1] mcs master clock select. this must match the ratio between the input mclk frequency and the audio sample rate, as shown in table 11 . 0x2 rw 0000 64 f s 0001 128 f s 0010 256 f s 0011 384 f s 0100 512 f s 0101 768 f s 0110 100 f s 0111 200 f s 1000 400 f s 1001 reserved 0 spwdn software master power-down. this places all blocks, except the i 2 c interface, into a low power state. 0x1 rw 0 normal operation 1 software master power-down www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 27 of 48 edge speed and clocking control register address: 0x01, reset: 0x00, name: edge_clock_control table 14. bit descriptions for edge_clock_control bits bit name settings description reset access [7:3] reserved reserved. 0x00 rw [2:1] edge edge rate control. this limits the edge rate of the switching output stage. the low emi operation modes reduce the edge speed, lowering emi and power efficiency. 0x0 rw 00 no edge rate control 01 low emi 10 lower emi 11 lowest emi 0 asr automatic sample rate detection. 0x0 rw 0 automatic detection enabled 1 manual sample rate selection given by fs field, bits[1:0] of register 0x02 www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 28 of 48 serial audio interface and sa mple rate control register address: 0x02, reset: 0x02, name: serial_interface_sample_rate_control table 15. bit descriptions for seri al_interface_sample_rate_control bits bit name settings description reset access 7 reserved reserved. 0x0 rw [6:5] sdata_fmt serial data format. only required if sai = 000. 0x0 rw 00 i2s standard; data is delayed by one bclk cycle 01 left justified 10 right justified, 24-bit data 11 right justified, 16-bit data [4:2] sai serial audio interface format. 0x0 rw 000 i 2 s, left justified, or right justified stereo (depending on sdata_fmt) 001 2-slot tdm 010 4-slot tdm 011 8-slot tdm 100 16-slot tdm 101 mono pcm 110 reserved 111 reserved [1:0] fs manual sample rate selection. only required if asr = 1 in register 0x01. 0x2 rw 00 8 khz to 12 khz 01 16 khz to 24 khz 10 32 khz to 48 khz 11 64 khz to 96 khz www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 29 of 48 serial audio interface control register address: 0x03, reset: 0x00, name: serial_interface_control table 16. bit descriptions for serial_interface_control bits bit name settings description reset access 7 bclk_gen internal bclk generator enable. 0x0 rw 0 bit clock from bclk pin is used 1 internally generated bit clock is used 6 lrclk_mode lrclk shape selection. required only for tdm modes. 0x0 rw 0 50% duty cycle 1 1-bit pulse 5 lrclk_pol lrclk polarity. 0x0 rw 0 rising edge (normal) 1 falling edge (inverted) 4 sai_msb serial data bit order. 0x0 rw 0 msb first 1 lsb first [3:2] slot_width tdm slot width. required only for tdm modes. 0x0 rw 00 32 bclk cycles per slot 01 24 bclk cycles per slot 10 16 bclk cycles per slot 11 reserved 1 bclk_edge bclk active edge. 0x0 rw 0 rising bclk edge used 1 falling bclk edge used 0 reserved reserved. 0x0 rw www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 30 of 48 channel mapping control register address: 0x04, reset: 0x10, name: channel_mapping_control table 17. bit descriptions for channel_mapping_control bits bit name settings description reset access [7:4] ch_sel_r right channel select. channel 0 valid when running in mono (pcm) mode. 0x1 rw channel 0 to channel 1 valid when running in stereo and 2-slot tdm modes. channel 0 to channel 3 valid when running in 4-slot tdm mode. channel 0 to channel 7 valid when running in 8-slot tdm mode. channel 0 to channel 15 valid when running in 16-slot tdm mode. 0000 channel 0 0001 channel 1 0010 channel 2 0011 channel 3 0100 channel 4 0101 channel 5 0110 channel 6 0111 channel 7 1000 channel 8 1001 channel 9 1010 channel 10 1011 channel 11 1100 channel 12 1101 channel 13 1110 channel 14 1111 channel 15 [3:0] ch_sel_l left channel select. channel 0 va lid when running in mono (pcm) mode. 0x0 rw channel 0 to channel 1 valid when running in stereo and 2-slot tdm modes. channel 0 to channel 3 valid when running in 4-slot tdm mode. channel 0 to channel 7 valid when running in 8-slot tdm mode. channel 0 to channel 15 valid when running in 16-slot tdm mode. 0000 channel 0 0001 channel 1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 31 of 48 bits bit name settings description reset access 0010 channel 2 0011 channel 3 0100 channel 4 0101 channel 5 0110 channel 6 0111 channel 7 1000 channel 8 1001 channel 9 1010 channel 10 1011 channel 11 1100 channel 12 1101 channel 13 1110 channel 14 1111 channel 15 left channel volume control register address: 0x05, reset: 0x40, name: left_volume_control table 18. bit descriptions for left_volume_control bits bit name settings description reset access [7:0] l_vol left channel volume control. adjusts the digital gain in 0.375 db increments. 0x40 rw 00000000 +24 db 00000001 +23.625 db 00000010 +23.35 db 00000011 +22.875 db 00000100 +22.5 db 00000101 +22.125 db 00111111 +0.375 db 01000000 0 db 01000001 ?0.375 db 01000010 ?0.750 db 11111101 ?70.875 db 11111110 ?71.25 db 11111111 mute www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 32 of 48 right channel volume control register address: 0x06, reset: 0x40, name: right_volume_control table 19. bit descriptions for right_volume_control bits bit name settings description reset access [7:0] r_vol right channel volume control. adjusts the digital gain in 0.375 db increments. 0x40 rw 00000000 +24 db 00000001 +23.625 db 00000010 +23.35 db 00000011 +22.875 db 00000100 +22.5 db 00000101 +22.125 db 00111111 +0.375 db 01000000 0 db 01000001 ?0.375 db 01000010 ?0.750 db 11111101 ?70.875 db 11111110 ?71.25 db 11111111 mute www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 33 of 48 volume and mute control register address: 0x07, reset: 0x81, name: volume_mute_control table 20. bit descriptions for volume_mute_control bits bit name settings description reset access 7 amute automatic mute enable. after 2048 slots (1024 stereo samples) have been received with zero data, the outputs mute until nonzero data arrives. 0x1 rw 0 automute enabled 1 automute disabled 6 reserved reserved. 0x0 rw 5 ana_gain analog gain. this sets the full-scale output level of the amplifier. the two settings are scaled appropriately fo r 3.6 v and 5.0 v nominal supply voltages. 0x0 rw 0 matched to 3.6 v supply 1 matched to 5.0 v supply 4 deemp_en digital de-emphasis filter. 0x0 rw 0 de-emphasis disabled (normal operation) 1 de-emphasis enabled 3 vol_link volume link. when this bit is enabled, both channels respond to the left channel volume register. 0x0 rw 0 normal operation 1 both channels linked to l_vol (register 0x05) 2 r_mute right channel soft mute. 0x0 rw 0 normal operation 1 right channel muted 1 l_mute left channel soft mute. 0x0 rw 0 normal operation 1 left channel muted 0 m_mute master mute control. this bit soft mutes both channels. 0x1 rw 0 normal operation 1 master mute www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 34 of 48 fault control 1 register address: 0x08, reset: 0x0c, name: fault_control_1 table 21. bit descriptions for fault_control_1 bits bit name settings description reset access 7 oc_l left channel overcurrent fault. read only. 0x0 r 0 normal operation 1 left channel overcurrent fault 6 oc_r right channel overcurrent fault. read only. 0x0 r 0 normal operation 1 right channel overcurrent fault 5 ot overtemperature fault status. read only. 0x0 r 0 normal operation 1 overtemperature fault 4 mrcv manual fault recovery. available only when arcv = 11. write only. 0x0 w 0 normal operation 1 when written, attempt a manual fault recovery [3:2] max_ar maximum fault recovery attempts. 0x3 rw 00 one attempt 01 three attempts 10 seven attempts 11 unlimited attempts [1:0] arcv automatic fault recovery selection. 0x0 rw 00 automatically recover from overtemperature and overcurrent faults 01 automatically recover from overtemperature fault only 10 automatically recover from overcurrent faults only 11 no automatic recovery www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 35 of 48 power and fault control register address: 0x09, reset: 0x99, name: power_fault_control table 22. bit descriptions for power_fault_control bits bit name settings description reset access [7:6] ar_time automatic recovery delay time. this determines the amount of time delay between fault detection and an autorecovery attempt. 0x2 rw 00 10 ms autorecovery delay 01 20 ms autorecovery delay 10 40 ms autorecovery delay 11 80 ms autorecovery delay 5 reserved reserved. 0x0 rw 4 amp_lpm class-d amplifier low power mode. 0x1 rw 0 high performance operation 1 low power operation 3 dac_lpm dac low power mode. in low power mode, the dac runs at half speed. 0x1 rw 0 normal operation 1 low power operation 2 r_pwdn right channel power-down. 0x0 rw 0 normal operation 1 right channel powered down 1 l_pwdn left channel power-down. 0x0 rw 0 normal operation 1 left channel powered down 0 apwdn_en automatic power-down enable. automatic power-down automatically puts the ic in a low power state when 2048 consecutive zero input samples have been received. 0x1 rw 0 automatic power-down disabled 1 automatic power-down enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 36 of 48 drc control 1 register address: 0x0a, reset: 0x7c, name: drc_control_1 table 23. bit descriptions for drc_control_1 bits bit name settings description reset access 7 reserved reserved. 0x0 rw 6 pre_vol drc placement. this determines the placement of the drc block in the signal chain. when placed before the volume control, the thresholds are relative to the input signal. when placed after the volume control, the thresholds are relative to the output si gnal level. all thresholds are 6 db higher when placed after the volume control. 0x1 rw 0 drc operates after the volume control 1 drc operates before the volume control 5 lim_en limiter enable. with the limiter enable d, the drc_lt threshold (bits[7:4] in register 0x0c) must be set. 0x1 rw 0 limiter disabled 1 limiter enabled 4 comp_en compressor enable. with the co mpressor enabled, the drc_ct and drc_smax thresholds (bits[3:0] in register 0x0c and bits[7:4] in register 0x0e) must be set. 0x1 rw 0 compressor disabled 1 compressor enabled 3 exp_en expander enable. with the expander enabled, the drc_et and drc_smin threshold values (bits[7:4] in register 0x0d and bits[3:0] in register 0x0e) must be set. 0x1 rw 0 expander disabled 1 expander enabled 2 ng_en noise gate enable. with the noise gate enabled, the drc_nt threshold value (bits[3:0] in register 0x0d) must be set. 0x1 rw 0 noise gate disabled 1 noise gate enabled [1:0] drc_en master drc enable. this must be enab led for any of the drc features to function. 0x0 rw 00 drc disabled 01 left channel drc enabled 10 right channel drc enabled 11 left and right channel drc enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 37 of 48 drc control 2 register address: 0x0b, reset: 0x5b, name: drc_control_2 table 24. bit descriptions for drc_control_2 bits bit name settings description reset access [7:4] peak_att drc peak detector attack time. 0x5 rw 0000 0 ms 0001 0.09 ms 0010 0.19 ms 0011 0.37 ms 0100 0.75 ms 0101 1.5 ms 0110 3 ms 0111 6 ms 1000 12 ms 1001 24 ms 1010 48 ms 1011 96 ms 1100 192 ms 1101 384 ms 1110 768 ms 1111 1.536 sec [3:0] peak_rel drc peak detector release time. 0xb rw 0000 0 ms 0001 1.5 ms 0010 3 ms 0011 6 ms 0100 12 ms 0101 24 ms 0110 48 ms 0111 96 ms www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 38 of 48 bits bit name settings description reset access 1000 193 ms 1001 384 ms 1010 768 ms 1011 1.536 sec 1100 3.072 sec 1101 6.144 sec 1110 12.288 sec 1111 24.576 sec drc control 3 register address: 0x0c, reset: 0x57, name: drc_control_3 table 25. bit descriptions for drc_control_3 bits bit name settings description reset access [7:4] drc_lt drc limiter threshold setting. relative to input. 0x5 rw 0000 0 db 0001 ?1 db 0010 ?2 db 0011 ?3 db 0100 ?4 db 0101 ?5 db 0110 ?6 db 0111 ?7 db 1000 ?8 db 1001 ?10 db 1010 ?12 db 1011 ?14 db 1100 ?16 db 1101 ?18 db 1110 ?20 db 1111 ?22 db www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 39 of 48 bits bit name settings description reset access [3:0] drc_ct drc compressor lower threshold setting. relative to input. 0x7 rw 0000 ?4 db 0001 ?6 db 0010 ?8 db 0011 ?10 db 0100 ?12 db 0101 ?14 db 0110 ?16 db 0111 ?18 db 1000 ?20 db 1001 ?22 db 1010 ?24 db 1011 ?26 db 1100 ?28 db 1101 ?30 db 1110 ?32 db 1111 ?34 db www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 40 of 48 drc control 4 register address: 0x0d, reset: 0x89, name: drc_control_4 table 26. bit descriptions for drc_control_4 bits bit name settings description reset access [7:4] drc_et drc expander upper threshol d setting. relative to input. 0x8 rw 0000 ?36 db 0001 ?39 db 0010 ?42 db 0011 ?45 db 0100 ?48 db 0101 ?51 db 0110 ?54 db 0111 ?57 db 1000 ?60 db 1001 ?63 db 1010 ?66 db 1011 ?69 db 1100 ?72 db 1101 ?75 db 1110 ?78 db 1111 ?81 db [3:0] drc_nt drc noise gate threshold setting. relative to input. 0x9 rw 0000 ?51 db 0001 ?54 db 0010 ?57 db 0011 ?60 db 0100 ?63 db 0101 ?66 db 0110 ?69 db 0111 ?72 db 1000 ?75 db 1001 ?78 db 1010 ?81 db 1011 ?84 db www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 41 of 48 bits bit name settings description reset access 1100 ?87 db 1101 ?90 db 1110 ?93 db 1111 ?96 db drc control 5 register address: 0x0e, reset: 0x8c, name: drc_control_5 table 27. bit descriptions for drc_control_5 bits bit name settings description reset access [7:4] drc_smax drc limiter threshold setting. relative to input. 0x8 rw 0000 0 db 0001 ?1 db 0010 ?2 db 0011 ?3 db 0100 ?4 db 0101 ?5 db 0110 ?6 db 0111 ?7 db 1000 ?8 db 1001 ?10 db 1010 ?12 db 1011 ?14 db 1100 ?16 db 1101 ?18 db 1110 ?20 db 1111 ?22 db www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 42 of 48 bits bit name settings description reset access [3:0] drc_smin drc minimum output signal ampli tude setting. this is the minimum output level produced by the drc and is used to indicate the expander lower threshold, or output signal level when the input rises beyond the noise gate threshold. 0xc rw 0000 ?51 db 0001 ?54 db 0010 ?57 db 0011 ?60 db 0100 ?63 db 0101 ?66 db 0110 ?69 db 0111 ?72 db 1000 ?75 db 1001 ?78 db 1010 ?81 db 1011 ?84 db 1100 ?87 db 1101 ?90 db 1110 ?93 db 1111 ?96 db drc control 6 register address: 0x0f, reset: 0x77, name: drc_control_6 table 28. bit descriptions for drc_control_6 bits bit name settings description reset access [7:4] drc_att drc attack time. used to smooth the gain curve at the thresholds (knees) of each drc function. 0x7 rw 0000 0 ms 0001 0.1 ms 0010 0.19 ms 0011 0.37 ms 0100 0.75 ms 0101 1.5 ms www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 43 of 48 bits bit name settings description reset access 0110 3 ms 0111 6 ms 1000 12 ms 1001 24 ms 1010 48 ms 1011 96 ms 1100 192 ms 1101 384 ms 1110 768 ms 1111 1.536 sec [3:0] drc_dec drc decay time. used to smooth the gain curve at the thresholds (knees) of each drc function. 0x7 rw 0000 0 ms 0001 1.5 ms 0010 3 ms 0011 6 ms 0100 12 ms 0101 24 ms 0110 48 ms 0111 96 ms 1000 192 ms 1001 384 ms 1010 768 ms 1011 1.536 sec 1100 3.072 sec 1101 6.144 sec 1110 12.288 sec 1111 24.576 sec www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 44 of 48 drc control 7 register address: 0x10, reset: 0x26, name: drc_control_7 table 29. bit descriptions for drc_control_7 bits bit name settings description reset access [7:4] hdt_nor drc normal operation hold time. used to prevent the gain curve calculation from increasing too quickly. 0x2 rw 0000 0 ms 0001 0.67 ms 0010 1.33 ms 0011 2.67 ms 0100 5.33 ms 0101 10.66 ms 0110 21.32 ms 0111 42.64 ms 1000 85.28 ms 1001 170.56 ms 1010 341.12 ms 1011 682.24 ms 1100 1.364 sec 1101 reserved 1110 reserved 1111 reserved [3:0] hdt_ng drc noise gate hold time. used to prevent the drc from entering noise gate too quickly. 0x6 rw 0000 0 ms 0001 0.67 ms 0010 1.33 ms 0011 2.67 ms 0100 5.33 ms 0101 10.66 ms 0110 21.32 ms 0111 42.64 ms 1000 85.28 ms 1001 170.56 ms www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 45 of 48 bits bit name settings description reset access 1010 341.12 ms 1011 682.24 ms 1100 1.364 sec 1101 reserved 1110 reserved 1111 reserved drc control 8 register address: 0x11, reset: 0x1c, name: drc_control_8 table 30. bit descriptions for drc_control_8 bits bit name settings description reset access [7:6] reserved reserved. 0x0 rw [5:2] drc_post_g post-drc gain adjust setting. this ca n be used to add additional gain after the drc function to compensate for the overall reduction of system gain due to the drc. 0x7 rw 0000 +21 db 0001 +18 db 0010 +15 db 0011 +12 db 0100 +9 db 0101 +6 db 0110 +3 db 0111 0 db 1000 ?3 db 1001 ?6 db 1010 ?9 db 1011 ?12 db 1100 ?15 db 1101 ?18 db 1110 ?21 db 1111 ?24 db [1:0] reserved reserved. 0x0 rw www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 46 of 48 drc control 9 register address: 0x12, reset: 0x07, name: drc_control_9 table 31. bit descriptions for drc_control_9 bits bit name settings description reset access [7:4] reserved reserved. 0x0 rw [3:0] rms_tav drc rms detector averaging time. this is the averaging time for the rms level that is compared to the drc thresholds. 0x7 rw 0000 0 ms 0001 1.5 ms 0010 3 ms 0011 6 ms 0100 12 ms 0101 24 ms 0110 48 ms 0111 96 ms 1000 192 ms 1001 384 ms 1010 768 ms 1011 1.536 sec 1100 3.072 sec 1101 6.144 sec 1110 12.288 sec 1111 24.576 sec www.datasheet.net/ datasheet pdf - http://www..co.kr/ data sheet SSM2518 rev. a | page 47 of 48 packaging and ordering information outline dimensions 05-19-2011-a a b c d 0.660 0.600 0.540 side view 0.270 0.240 0.210 0.360 0.320 0.280 coplanarity 0.05 seating plane 1 2 3 4 bottom view (ball side up) top view (ball side down) ball 1 identifier 0.50 ref 1.50 ref 2.250 2.210 sq 2.170 figure 37.16-ball wafer level chip scale package [wlcsp] (cb-16-13) dimensions shown in millimeters 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd. 061609-b bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 2.65 2.50 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 38. 20-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-20-10) dimensions shown in millimeters www.datasheet.net/ datasheet pdf - http://www..co.kr/ SSM2518 data sheet rev. a | page 48 of 48 ordering guide model 1 temperature range package description package option SSM2518cbz-rl ?40c to +85c 16-ball, 2.2 mm 2.2 mm wlcsp cb-16-13 SSM2518cbz-r7 ?40c to +85c 16-ball, 2.2 mm 2.2 mm wlcsp cb-16-13 SSM2518cpz ?40c to +85c 20-lead 4 mm 4 mm lfcsp cp-20-10 SSM2518cpz-r7 ?40c to +85c 20-lead 4 mm 4 mm lfcsp cp-20-10 SSM2518cpz-rl ?40c to +85c 20-lead 4 mm 4 mm lfcsp cp-20-10 eval-SSM2518z evaluation board 1 z = rohs compliant part. www.analog.com/SSM2518 ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10242-0-12/11(a) www.datasheet.net/ datasheet pdf - http://www..co.kr/ |
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